• Thermal Simulation

  • Thermal Strain

Software

Cadence Allegro Package Designer16.6
  • Package/pin-delay length report
  • Constraint Manager (electrical and physical)
ANSYS Mechanical v14.5
 
Mechanical Simulation

Strip/Unit Warpage, Solder Joint Reliability, Thermal Stress

Thermal Simulation
  • JA : Junction to Ambient Thermal Resistance
  • JC : Junction to Case Thermal Resistance

Thermal Modeling

Using JESD51 Standard for modeling
For Gaining an Accurate Results, Using Detail Model

Thermal Standards(EIA/JEDEC Standard)

JESD51-2
  • Integrated Circuits Thermal Test Method
  • Environment Conditions (Still Air)
JESD51-3
  • Low Effective Thermal Conductivity
  • Test Board for Leaded Surface Mount Packages
JESD51-7
  • High Effective Thermal Conductivity
  • Test Board for Leaded Surface Mount Packages
JESD51-8
  • Integrated Circuit Thermal Test Method
  • Environmental Conditions – Junction-to-Board
JESD51-9
  • Test Boards for Area Array Surface Mount
  • Package Thermal Measurements